Dynamic power is dominant component of the average power dissipation in cmos circuits . and the value of dynamic power is determined by node capacitance , supply voltage , clock frequency and switching activity of cmos circuits . so most low power designs are achieved by reducing one or more those above parameters 由于cmos电路的功耗与cmos电路的负载电容，电压，时钟频率及开关活动性有关，因此在低功耗cmos触发器设计过程中，许多低功耗设计技术都可以归结到通过减小上面的参数来达到低功耗的目的。
In this paper , low power flip - flops designs by the reduction of the load of clock or the data path ; by the reduction of clock swing ; by the reduction of clock frequency and by the reduction of those idle transitions in cmos circuits with clock gating are discussed 与此相对应的，在本论文中，分别对将少时钟负载或数据通路的负载的触发器设计；减小时钟信号幅度的触发器设计；降低时钟频率的双边沿触发器设计以及应用门控技术来减少触发器无效跳变设计的触发器结构进行了讨论。
Finally , th e design of low voltage low power current mode cmos circuit is discussed , the design is base on a novel structure which converts serial switches to parallel switches , allows the circuits to perform under lower source voltage which makes low power consuming possible , examples and simulation results are also given to prove the low power character can be reached 论文最后还讨论了低电压低功耗电流型cmos电路的设计，这一设计巧妙地将电路中的串联开关转换成并联开关，使电流型cmos电路能在更低的电源电压下工作，实现了电路的低功耗设计。论文中给出的设计实例和仿真结果验证了基于并联开关的电流型cmos电路的低功耗特性。
More recently , the advent of new soi wafer fabrication techniques and the explosive growth of portable microelectronic devices have attracted considerable attention on soi for the fabrication of low - power ( lp ) , low - voltage ( lv ) , and high - frequency ( hf ) cmos circuits . in this thesis , we study the electrical characterization on soi wafers and design a low - power soi cmos dram structure 第二部分我们对高性能低功耗soidram结构的设计进行了研究，设计了一个低压低功耗soidram阵列模型，介绍了我们的dram的逻辑结构设计，存储单元设计，存储器阵列的设计，及读写电路等外围电路的设计。
Two other effects are transient phenomenon called single event upset ( seu ) and single event latchup ( sel ) . in this paper , some means to harden the devices against these phenomena are used . guard banding around nmos and pmos transistors greatly reduces the susceptibility of cmos circuits to lachup 在本文设计中，采用双环保护结构，大大的降低了cmos集成电路对单粒子闩锁效应的敏感性；对nmos管采用环型栅结构代替传统的双边器件结构，消除了辐射感生边缘寄生晶体管漏电效应；采用附加晶体管的冗余锁存结构，减轻了单粒子翻转效应的影响。
In the early 1980 ’ s , quiescent power supply current ( iddq ) testing method was proposed in cmos testing . testing method based on current testing have very good compatibility with cmos circuits , it can detect some faults and physical defects those cannot be detected by testing methods based on voltage testing 基于电流的iddq测试方法与cmos电路有很好的兼容性,它可检测出电压测试方法不能检测的故障和物理缺陷,目前已成为一种广为接受的重要的cmos数字集成电路的测试方法。
